The present application relates generally to semiconductor devices, and particularly to vertical fin field effect transistors (V-FinFETs) and their methods of fabrication.
Fully-depleted devices such as fin field effect transistors (FinFETs) are candidates to enable scaling of next generation gate lengths to 14 nm and below. Fin field effect transistors (FinFETs) present a three-dimensional architecture where the transistor channel is raised above the surface of a semiconductor substrate, rather than locating the channel at or just below the surface. With a raised channel, the gate can be wrapped around the sides of the channel, which provides improved electrostatic control of the device.
The manufacture of FinFETs typically leverages a self-aligned process to produce extremely thin fins, e.g., 20 nm wide or less, on the surface of a substrate using selective-etching techniques. A gate structure is then deposited to contact multiple surfaces of each fin to form a multi-gate architecture.
Vertical FETs are devices where the source-drain current flows in a direction normal to the substrate surface. In vertical FinFET devices, the fin defines the transistor channel with the source and drain regions located at opposing (i.e., upper and lower) ends of the fin.
A challenge associated with a vertical FET architecture is precise control of the fidelity of a fin cut, e.g., to form discrete devices amongst plural segments of an incumbent fin. In various conventional approaches, such as a fin cut first approach, successive masking and etching steps are used to form a fin-defining hard mask over a semiconductor substrate, selectively remove unwanted portions of the hard mask, and then etch the semiconductor substrate using the patterned hard mask as an etch mask to form a plurality of cut fins. In addition to the challenge of accurately locating the resulting fins, i.e., within designated active regions of the substrate, the thickness of the hard mask used to define the fins can challenge the formation of fins with the desired geometry, including substantially vertical sidewalls. Accordingly, it would be advantageous to provide a robust, vertical FinFET manufacturing process and associated structure that are compatible with existing circuit designs, while enabling precise dimensional control of severed fins.